Best for
- Use when developing firmware for microcontrollers, implementing RTOS applications, or optimizing power consumption.
Jeffallan/claude-skills/skills/embedded-systems/SKILL.md
Use when developing firmware for microcontrollers, implementing RTOS applications, or optimizing power consumption. Invoke for STM32, ESP32, FreeRTOS, bare-metal, power optimization, real-time systems, configure peripherals, write interrupt handlers, implement DMA transfers, debug timing issues.
Decision brief
Senior embedded systems engineer with deep expertise in microcontroller programming, RTOS implementation, and hardware-software integration for resource-constrained devices.
Compatibility matrix
| Platform | Status | Evidence | What to check |
|---|---|---|---|
| Codex | Not declared | No explicit evidence | Portability before use |
| Claude Code | Not declared | No explicit evidence | Portability before use |
| Cursor | Not declared | No explicit evidence | Portability before use |
| Gemini CLI | Not declared | No explicit evidence | Portability before use |
Installation
The source command is displayed only when detected. A safe inspection prompt is always available so your agent can explain every action before execution.
npx skills add https://github.com/Jeffallan/claude-skills --skill "skills/embedded-systems"Inspect the Agent Skill "embedded-systems" from https://github.com/Jeffallan/claude-skills/blob/e8be415bc94d8d6ebddc2fb50e5d03c6e27d4319/skills/embedded-systems/SKILL.md at commit e8be415bc94d8d6ebddc2fb50e5d03c6e27d4319. List every install step, command, network request, credential, file read/write, external action, and rollback step. Explain whether it fits my task. Do not install or execute anything until I approve.
Workflow
1. Analyze constraints - Identify MCU specs, memory limits, timing requirements, power budget 2. Design architecture - Plan task structure, interrupts, peripherals, memory layout 3. Implement drivers - Write HAL, peripheral drivers, RTOS integration 4. Validate implementation -…
Load detailed guidance based on context:
Optimize for code size and RAM usage
Optimize for code size and RAM usage
Use blocking operations in ISRs
Permission review
No configured static risk pattern was detected
This is not proof of safety. Runtime behavior, indirect dependencies, and hidden external systems are outside the static scan.
Evidence record
| Signal | Value | Evidence type | Meaning |
|---|---|---|---|
| Quality score | 83/100 | Computed | Documentation, specificity, maintenance, and trust rules |
| Repository stars | 10,762 | Source | Repository attention, not individual Skill quality |
| Compatibility | 0 platforms | Source | Declared in the catalog source record |
| Usage guide | automated source guide | Editorial | Generated or reviewed according to the visible evidence level |
Pinned source
Senior embedded systems engineer with deep expertise in microcontroller programming, RTOS implementation, and hardware-software integration for resource-constrained devices.
-Wall -Werror, verify no warnings; run static analysis (e.g. cppcheck); confirm correct register bit-field usage against datasheetuxTaskGetStackHighWaterMark(); measure ISR latency; confirm no missed deadlines under worst-case load; if issues found, return to step 4Load detailed guidance based on context:
| Topic | Reference | Load When |
|---|---|---|
| RTOS Patterns | references/rtos-patterns.md | FreeRTOS tasks, queues, synchronization |
| Microcontroller | references/microcontroller-programming.md | Bare-metal, registers, peripherals, interrupts |
| Power Management | references/power-optimization.md | Sleep modes, low-power design, battery life |
| Communication | references/communication-protocols.md | I2C, SPI, UART, CAN implementation |
| Memory & Performance | references/memory-optimization.md | Code size, RAM usage, flash management |
volatile for hardware registers and ISR-shared variables/* Flag shared between ISR and task — must be volatile */
static volatile uint8_t g_uart_rx_flag = 0;
static volatile uint8_t g_uart_rx_byte = 0;
/* Keep ISR short: read hardware, set flag, exit */
void USART2_IRQHandler(void) {
if (USART2->SR & USART_SR_RXNE) {
g_uart_rx_byte = (uint8_t)(USART2->DR & 0xFF); /* clears RXNE */
g_uart_rx_flag = 1;
}
}
/* Main loop or RTOS task processes the flag */
void process_uart(void) {
if (g_uart_rx_flag) {
__disable_irq(); /* enter critical section */
uint8_t byte = g_uart_rx_byte;
g_uart_rx_flag = 0;
__enable_irq(); /* exit critical section */
handle_byte(byte);
}
}
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#define SENSOR_TASK_STACK 256 /* words */
#define SENSOR_TASK_PRIO 2
static QueueHandle_t xSensorQueue;
static void vSensorTask(void *pvParameters) {
TickType_t xLastWakeTime = xTaskGetTickCount();
const TickType_t xPeriod = pdMS_TO_TICKS(10); /* 10 ms period */
for (;;) {
/* Periodic, deadline-driven read */
uint16_t raw = adc_read_channel(ADC_CH0);
xQueueSend(xSensorQueue, &raw, 0); /* non-blocking send */
/* Check stack headroom in debug builds */
configASSERT(uxTaskGetStackHighWaterMark(NULL) > 32);
vTaskDelayUntil(&xLastWakeTime, xPeriod);
}
}
void app_init(void) {
xSensorQueue = xQueueCreate(8, sizeof(uint16_t));
configASSERT(xSensorQueue != NULL);
xTaskCreate(vSensorTask, "Sensor", SENSOR_TASK_STACK,
NULL, SENSOR_TASK_PRIO, NULL);
vTaskStartScheduler();
}
/* Demonstrates: clock enable, register-level GPIO, TIM2 interrupt */
#include "stm32f4xx.h"
void TIM2_IRQHandler(void) {
if (TIM2->SR & TIM_SR_UIF) {
TIM2->SR &= ~TIM_SR_UIF; /* clear update flag */
GPIOA->ODR ^= GPIO_ODR_OD5; /* toggle LED on PA5 */
}
}
void blink_init(void) {
/* GPIO */
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
GPIOA->MODER |= GPIO_MODER_MODER5_0; /* PA5 output */
/* TIM2 @ ~1 Hz (84 MHz APB1 × 2 = 84 MHz timer clock) */
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
TIM2->PSC = 8399; /* /8400 → 10 kHz */
TIM2->ARR = 9999; /* /10000 → 1 Hz */
TIM2->DIER |= TIM_DIER_UIE;
TIM2->CR1 |= TIM_CR1_CEN;
NVIC_SetPriority(TIM2_IRQn, 6);
NVIC_EnableIRQ(TIM2_IRQn);
}
When implementing embedded features, provide:
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